F-Tile Serial Lite IV Intel® FPGA IP User Guide

ID 683074
Date 6/21/2022

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Document Table of Contents Start-of-burst CW

Figure 11. Start-of-burst CW Format
In Full mode, you can insert the START CW by asserting the tx_avs_startofpacket signal. When you assert only the tx_avs_startofpacket signal, the sop bit is set. When you assert both the tx_avs_startofpacket and tx_avs_endofpacket signals, the seop bit is set.
Table 13.   START CW Field Values
Field Value
sop/seop 1
usr 8 Depending on the tx_is_usr_cmd signal:
  • 1: When tx_is_usr_cmd = 1
  • 0: When tx_is_usr_cmd = 0
align 0

In Basic mode, the MAC sends a START CW after the reset is deasserted. If no data is available, the MAC continuously sends EMPTY_CYC paired with END and START CWs until you start sending data.

8 This is supported only in Full mode.