2.4. Register Map
Note:
- The register addresses listed in this section are 32-bit word address.
- Interlaken IP core register base address is 0x2000000.
- Design Example register base address is 0x4000000.
- F-tile PHY register base address is 0x6000000.
- F-tile FEC register base address is 0x8000000.
- Access code: RO—Read Only, and RW—Read/Write.
- System console reads the design example registers and reports the test status on the screen.
Offset | Name | Access | Description |
---|---|---|---|
8'h00 | Reserved | ||
8'h01 | Reserved | ||
8'h02 | System PLL reset | RO | Following bits indicates system PLL reset request and enable value:
|
8'h03 | RX lane aligned | RO | Indicates the RX lane alignment. |
8'h04 | WORD locked | RO | [NUM_LANES–1:0] – Word (block) boundaries identification. |
8'h05 | Sync locked | RO | [NUM_LANES–1:0] – Metaframe synchronization. |
8'h06 - 8'h09 | CRC32 error count | RO | Indicates the CRC32 error count. |
8'h0A | CRC24 error count | RO | Indicates the CRC24 error count. |
8'h0B | Overflow/Underflow signal | RO | Following bits indicate:
|
8'h0C | SOP count | RO | Indicates the number of SOP. |
8'h0D | EOP count | RO | Indicates the number of EOP |
8'h0E | Error count | RO | Indicates the number of following errors:
|
8'h0F | send_data_mm_clk | RW | Write 1 to bit [0] to enable the generator signal. |
8'h10 | Checker error | Indicates the checker error. (SOP data error, Channel number error, and PLD data error) | |
8'h11 | System PLL lock | RO | Bit [0] indicates PLL lock indication. |
8'h14 | TX SOP count | RO | Indicates number of SOP generated by the packet generator. |
8'h15 | TX EOP count | RO | Indicates number of EOP generated by the packet generator. |
8'h16 | Continuous packet | RW | Write 1 to bit [0] to enable the continuous packet. |
8'h39 | ECC error count | RO | Indicates number of uncorrectable ECC errors. |
8'h40 | ECC corrected error count | RO | Indicates number of corrected ECC errors. |
8’h50 | tile_tx_rst_n | WO | Tile reset to SRC for TX. |
8’h51 | tile_rx_rst_n | WO | Tile reset to SRC for RX. |
8’h52 | tile_tx_rst_ack_n | RO | Tile reset acknowledge from SRC for TX. |
8’h53 | tile_rx_rst_ack_n | RO | Tile reset acknowledge from SRC for RX. |
8'h54 | fec_snapshot | RW | This signal is only available in PAM4 mode with 32-bit soft cwbin counters enabled. fec_snapshot drives to the IP input. Write 1 to bit[0] to snapshot CWBIN counter CSRs. Write 0 to bit[0] to clear the collection and shadow counters. |
Offset | Name | Access | Description |
---|---|---|---|
8'h00 | Reserved | ||
8'h01 | Counter reset | RO | Write 1 to bit [0] to clear TX and RX counter equal bit. |
8'h02 | System PLL reset | RO | Following bits indicates system PLL reset request and enable value:
|
8'h03 | RX lane aligned | RO | Indicates the RX lane alignment. |
8'h04 | WORD locked | RO | [NUM_LANES–1:0] – Word (block) boundaries identification. |
8'h05 | Sync locked | RO | [NUM_LANES–1:0] – Metaframe synchronization. |
8'h06 - 8'h09 | CRC32 error count | RO | Indicates the CRC32 error count. |
8'h0A | CRC24 error count | RO | Indicates the CRC24 error count. |
8'h0B | Reserved | ||
8'h0C | SOP count | RO | Indicates the number of SOP. |
8'h0D | EOP count | RO | Indicates the number of EOP |
8'h0E | Error count | RO | Indicates the number of following errors:
|
8'h0F | send_data_mm_clk | RW | Write 1 to bit [0] to enable the generator signal. |
8'h10 | Checker error | RO | Indicates the checker error. (SOP data error, Channel number error, and PLD data error) |
8'h11 | System PLL lock | RO | Bit [0] indicates PLL lock indication. |
8'h13 | Latency count | RO | Indicates number of latency. |
8'h14 | TX SOP count | RO | Indicates number of SOP generated by the packet generator. |
8'h15 | TX EOP count | RO | Indicates number of EOP generated by the packet generator. |
8'h16 | Continuous packet | RO | Write 1 to bit [0] to enable the continuous packet. |
8'h17 | TX and RX counter equal | RW | Indicates TX and RX counter are equal. |
8'h23 | Enable latency | WO | Write 1 to bit [0] to enable latency measurement. |
8'h24 | Latency ready | RO | Indicates latency measurement are ready. |
8’h50 | tile_tx_rst_n | WO | Tile reset to SRC for TX. |
8’h51 | tile_rx_rst_n | WO | Tile reset to SRC for RX. |
8’h52 | tile_tx_rst_ack_n | RO | Tile reset acknowledge from SRC for TX. |
8’h53 | tile_rx_rst_ack_n | RO | Tile reset acknowledge from SRC for RX. |
8'h54 | fec_snapshot | RW | This signal is only available in PAM4 mode with 32-bit soft cwbin counters enabled. fec_snapshot drives to the IP input. Write 1 to bit[0] to snapshot the CWBIN counter CSRs. Write 0 to bit[0] to clear the collection and shadow counters. |