- Updated the figure Example Design Tab.
- Updated step 9 of the Generating the Design section.
- Updated the Note at the beginning of the Register Map section.
- Updated the product family name to "Intel Agilex 7."
- Register Map: New register information "fec_snapshot" added in the following tables:
- Design Example Register Map
- Design Example Register Map for Interlaken Look-aside Design Example
- Quick Start Guide: IP Supported Combinations of Number of Lanes and Data Rates table updated
- Generating the Design: Note added about VSR mode setting at the end of the section
- Compiling and Configuring the Hardware Design Example: Minor corrections in Step 4(b). PAM changed to PAM4. 166.66 MHz changed to 156.25 MHz
- Testing the Hardware Design Example: Note added in Step 4(c)
- Updated the development kit device part numbers in section: Generating the Design.
- Updated the Figure: Directory Structure.
- Updated the steps in section: Compiling and Configuring the Hardware Design Example.
- Added the external serial loopback support for FHT PMA.
- Updated the section: Interface Signals with:
- pll_ref_clk signal description
- New signals:
- Added the FHT PMA support for PAM4 variants.
- Updated commands in section: Testing the Hardware Design Example.
- Added support for the Interlaken Look-aside mode for all variants.
- Removed support for the ModelSim* SE simulator.
- Added support for the Cadence* Xcelium* simulator.
- Added support for the Interlaken Look-aside mode for three variants:
- 6 x 53.125G
- 12 x 12.5G
- 12 x 25.78125G
- Added hardware support for the F-tile Interlaken Intel® FPGA IP Design Example.
- Added support for new lane rate combinations. For more information, refer to Table: IP Supported Combinations of Number of Lanes and Data Rate.
- Updated the supported simulator list in section: Hardware and Software Requirements.
- Added new reset registers in section: Register Map.