F-Tile Interlaken Intel® FPGA IP Design Example User Guide

ID 683069
Date 6/26/2023
Public

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1.3. Directory Structure

The F-Tile Interlaken Intel® FPGA IP core generates the following files for the design example:
Figure 5. Directory Structure
Table 2.  Hardware Design Example File DescriptionsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design directory.
File Names Description
example_design.qpf Intel® Quartus® Prime project file.
example_design.qsf Intel® Quartus® Prime project settings file
example_design.sdc

jtag_timing_template.sdc

Synopsys* Design Constraint file. You can copy and modify for your own design.
sysconsole_testbench.tcl Main file for accessing System Console.

File location: <design_example_installation_dir>/ilk_f_0_example_design/example_design/hwtest

Table 3.  Testbench File DescriptionThis file is in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/rtl directory.
File Name Description
top_tb.sv Top-level testbench file.
Table 4.  Testbench ScriptsThese files are in the <design_example_installation_dir>/ilk_f_0_example_design/example_design/testbench directory.
File Name Description
run_vcs.sh The Synopsys* VCS* script to run the testbench.
run_vcsmx.sh The Synopsys* VCS* MX script to run the testbench.
run_mentor.tcl The Siemens* EDA QuestaSim* script to run the testbench.
run_xcelium.sh The Cadence* Xcelium* script to run the testbench.