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1.6. Testing the Hardware Design Example
After you compile the F-tile Interlaken Intel® FPGA IP design example and configure your device, you can use the System Console to program the IP core and its registers.
Follow these steps to bring up the System Console and test the hardware design example:
- In the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
- Change to the <design_example_installation_dir>example_design/hwtest directory.
- To open a connection to the JTAG master, type the following command:
source sysconsole_testbench.tcl
- You can turn on internal serial loopback mode with the following design example commands:
- stat: Prints general status info.
- sys_reset: Resets the system.
- run_example_design: Runs the example design with internal serial loopback.
- To run internal serial loopback on FHT PMA, use run_example_design_fht command.
- To run external loopback on FGT PMA, use run_example_design_exlb command.
Note: The Intel® Quartus® Prime Pro Edition software version 22.2 does not support the external serial loopback for FHT PMA.
- You can program the IP core with the following additional design example commands:
- gen_on: Enables the packet generator.
- gen_off: Disables the packet generator.
- sys_reset: System reset.
- clear_err: Clears all the CSR sticky error bits.
- clear_err_crc: Clears the Design Example CRC error flags.
- set_burst_size <burst_size>: Sets burst size in bytes. Acceptable values are 128, 256, or 512.
- get_burst_size: Prints burst size information.
The successful test prints HW_TEST:PASS message. Below is the passing criteria for a test run:- No errors for CRC32, CRC24, and checker.
- Transmitted SOPs and EOPs should match with the received SOPs and EOPs.
__________________________________________________________ INFO: INFO: Stop generating packtes __________________________________________________________ ==== STATUS REPORT ==== TX KHz : 366209 RX KHz : 366210 Freq locks : 0x00000f TX PLL lock : 0x000001 Align : 0x00d10f Rx LOA : 0x000000 Tx LOA : 0x000000 word lock : 0x00000f sync lock : 0x00000f CRC32 errors : 0 CRC24 errors : 0 Checker errors : 0 FIFO err flags : 0x000000 SOPs transmitted : 1866062873 EOPs transmitted : 1866062873 SOPs received : 1866062873 EOPs received : 1866062873 ECC corrected : 0 ECC error : 0 Elapsed 161 sec since powerup HW_TEST : PASS
The following sample output illustrates a successful test run in Interlaken Look-aside mode:__________________________________________________________ INFO: INFO: Stop generating packtes __________________________________________________________ ==== STATUS REPORT ==== TX KHz : 195312 RX KHz : 195312 Freq locks : 0x000fff TX PLL lock : 0x000001 Align : 0x00d10f Rx LOA : 0x000000 Tx LOA : 0x000000 word lock : 0x000fff sync lock : 0x000fff CRC32 errors : 0 CRC24 errors : 0 Checker errors : 0 FIFO err flags : 0x000000 SOPs transmitted : 3314317815 EOPs transmitted : 3314317815 SOPs received : 3314317815 EOPs received : 3314317815 Elapsed 163 sec since powerup HW_TEST : PASS