1.2. Generating the Design
Figure 3. Procedure
Follow these steps to generate the design example and testbench:
- Specify the device family Agilex and select device with F-Tile for your design.
Note: In the F-Tile Interlaken Intel FPGA IP design example, a SystemPLL is instantiated automatically, and connected to F-Tile Interlaken Intel FPGA IP core. The SystemPLL hierarchy path in the design example is:
example_design.test_env_inst.test_dut.dut.pll
The SystemPLL in the design example shares the same 156.26 MHz reference clock as the Transceiver.
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