Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon Streaming Hard IP for PCIe* Design Example User Guide

ID 683065
Date 1/13/2022

2.5. Registers

There are no control registers for the PIO design example. The PCI Express Base Specification 3.0 defines a comprehensive set of configuration, control, and status registers to control and debug the design example.

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