Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon Streaming Hard IP for PCIe* Design Example User Guide

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ID 683065
Date 1/13/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Functional Description 2.2. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.3. Intel® Arria® 10 Development Kit Conduit Interface 2.4. Serial Data Signals 2.5. Registers
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide

2.3. Intel® Arria® 10 Development Kit Conduit Interface

The Intel® Arria® 10 Development Kit conduit interface signals are optional signals that allow you to connect your design to the Intel® Arria® 10 FPGA Development Kit. Enable this interface by selecting Enable Intel® Arria® 10 FPGA Development Kit connection on the Configuration, Debug, and Extension Options tab of the component GUI. The devkit_status output port includes signals useful for debugging.
Table 2.  The Intel® Arria® 10 Development Kit Conduit Interface
Signal Name Direction Description
devkit_status[255:0] Output The devkit_status[255:0] bus comprises the following status signals :
  • devkit_status[1:0]: current_speed
  • devkit_status[2]: derr_cor_ext_rcv
  • devkit_status[3]: derr_cor_ext_rpl
  • devkit_status[4]: derr_err
  • devkit_status[5]: rx_par_err
  • devkit_status[7:6]: tx_par_err
  • devkit_status[8]: cfg_par_err
  • devkit_status[9]: dlup
  • devkit_status[10]: dlup_exit
  • devkit_status[11]: ev128ns
  • devkit_status[12]: ev1us
  • devkit_status[13]: hotrst_exit
  • devkit_status[17:14]: int_status[3:0]
  • devkit_status[18]: l2_exit
  • devkit_status[22:19]: lane_act[3:0]
  • devkit_status[27:23]: ltssmstate[4:0]
  • devkit_status[35:28]: ko_cpl_spc_header[7:0]
  • devkit_status[47:36]: ko_cpl_spc_data[11:0]
  • devkit_status[48]: rxfc_cplbuf_ovf
  • devkit_status[49]: reset_status
  • devkit_status[255:50]: Reserved
devkit_ctrl[255:0] Input The devkit_ctrl[255:0] bus comprises the following status signals. You can optionally connect these pins to an on-board switch for PCI-SIG compliance testing, such as bypass compliance testing.
  • devkit_ctrl[0]: test_in[0] is typically set to 1'b0
  • devkit_ctrl[4:1]: test_in[4:1] is typically set to 4'b0100
  • devkit_ctrl[6:5]: test_in[6:5] is typically set to 2'b01
  • devkit_ctrl[31:7]: test_in[31:7] is typically set to 25'h3
  • devkit_ctrl[63:32]: is typically set to 32'b0
  • devkit_ctrl[255:64]: is typically set to 192'b0
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