Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon Streaming Hard IP for PCIe* Design Example User Guide

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ID 683065
Date 1/13/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Functional Description 2.2. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.3. Intel® Arria® 10 Development Kit Conduit Interface 2.4. Serial Data Signals 2.5. Registers
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide

1.5. Compiling and Testing the Design in Hardware

Figure 8. Procedure
Figure 9. Software Application to Test the PCI Express Design Example on the Intel® Arria® 10 GX FPGA Development KitA software application running on a Windows PC performs the same hardware test for all of the PCI Express Design Examples.

The software application to test the PCI Express Design Example on the Intel® Arria® 10 GX FPGA Development Kit is available on both 32- and 64-bit Windows 7 platforms. This program performs the following tasks:

  1. Prints the Configuration Space, lane rate, and lane width.
  2. Writes 0x00000000 to the specified BAR at offset 0x00000000 to initialize the memory and read it back.
  3. Writes 0xABCD1234 at offset 0x00000000 of the specified BAR. Reads it back and compares.

If successful, the test program displays the message 'PASSED'

Follow these steps to compile the design example in the Quartus Prime software:

  1. Launch the Quartus Prime software and open the pcie_example_design.qpf file for the example design created above.
  2. On the Processing > menu, select Start Compilation.

    The timing constraints for the design example and the design components are automatically loaded during compilation.

Follow these steps to test the design example in hardware:

  1. In the <example_design>/software/windows/interop directory, unzip Altera_PCIe_Interop_Test.zip.
    Note: You can also refer to readme_Altera_PCIe_interop_Test.txt file in this same directory for instructions on running the hardware test.
  2. Install the Intel® FPGA Windows Demo Driver for PCIe on the Windows host machine, using altera_pcie_win_driver.inf.
    Note: If you modified the default Vendor ID (0x1172) or Device ID (0x0000) specified in the component parameter editor GUI, you must also modify them in altera_pcie_win_driver.inf.
    1. In the <example_design> directory, launch the Quartus Prime software and compile the design (Processing > Start Compilation).
    2. Connect the development board to the host computer.
    3. Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).
    4. Open the Windows Device Manager and scan for hardware changes.
    5. Select the Intel® FPGA listed as an unknown PCI device and point to the appropriate 32- or 64-bit driver (altera_pice_win_driver.inf) in the Windows_driver directory.
    6. After the driver loads successfully, a new device named Altera PCI API Device appears in the Windows Device Manager.
    7. Determine the bus, device, and function number for the Altera PCI API Device listed in the Windows Device Manager.
      1. Expand the tab, Altera PCI API Driver under the devices.
      2. Right click on Altera PCI API Device and select Properties.
      3. Note the bus, device, and function number for the device. The following figure shows one example.
      Figure 10. Determining the Bus, Device, and Function Number for New PCIe Device
  3. In the <example_design>/software/windows/interop/Altera_PCIe_Interop_Test/Interop_software directory, click Alt_Test.exe.
  4. When prompted, type the bus, device, and function numbers and select the BAR number (0-5) you specified when parameterizing the IP core.
    Note: The bus, device, and function numbers for your hardware setup may be different.
  5. The test displays the message, PASSED, if the test is successful.
Note: For more details on additional design implementation steps such as making pin assignments and adding timing constraints, refer to the Design Implementation chapter.
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