P-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide
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Visible to Intel only — GUID: aez1568148552381
Ixiasoft
3.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x104190)
When an error is detected, Intel recommends that you read the PF0 AER register inside P-Tile to get detailed information about the error. To clear the previous error status, you need to clear TLPBYPASS_ERR_STATUS and the corresponding correctable and uncorrectable error status registers in the AER capability structure. After doing that, you can get the new error update from this register.
Name | Bits | Reset Value | Access Mode | Register Description |
---|---|---|---|---|
Reserved | [31:20] | 12’b0 | RO | Reserved |
cfg_uncor_internal_err_sts | [19] | 1'b0 | W1C | Uncorrectable Internal Error |
cfg_corrected_internal_err_sts | [18] | 1'b0 | W1C | Corrected Internal Error |
cfg_rcvr_overflow_err_sts | [17] | 1'b0 | W1C | Receiver Overflow Error |
cfg_fc_protocol_err_sts | [16] | 1'b0 | W1C | Flow Control Protocol Error |
cfg_mlf_tlp_err_sts | [15] | 1'b0 | W1C | Malformed TLP Error |
cfg_surprise_down_err_sts | [14] | 1'b0 | W1C | Surprise Down Error. Available in downstream mode only. |
cfg_dl_protocol_err_sts | [13] | 1'b0 | W1C | Data Link Protocol Error |
cfg_replay_number_rollover_err_sts | [12] | 1'b0 | W1C | REPLAY_NUM Rollover Error |
cfg_replay_timer_timeout_err_sts | [11] | 1'b0 | W1C | Replay Timer Timeout Error |
cfg_bad_dllp_err_sts | [10] | 1'b0 | W1C | Bad DLLP Error |
cfg_bad_tlp_err_sts | [9] | 1'b0 | W1C | Bad TLP Error |
cfg_rcvr_err_sts | [8] | 1'b0 | W1C | Receiver Error |
Reserved | [7:1] | 7'b0 | RO | Reserved |
cfg_ecrc_err_sts | [0] | 1'b0 | W1C | ECRC Error |