- Four PCIe* cores (one x16 core, one x8 core and two x4 cores)
- Embedded Multi-die Interconnect Bridge (EMIB)
- Soft logic blocks in the FPGA fabric to implement functions such as VirtIO, etc.
The four cores in the PCIe Hard IP can be configured to support the following topologies:
|Configuration Mode||Native IP Mode||Endpoint (EP) / Root Port (RP) / TLP Bypass (BP)||Active Cores|
|Configuration Mode 0||Gen3 x16 or Gen4 x16||EP/RP/BP||x16|
|Configuration Mode 1||Gen3 x8/Gen3 x8 or Gen4 x8/Gen4 x8||EP/BP||x16, x8|
|Configuration Mode 2||Gen3 x4/Gen3 x4/Gen3 x4/Gen3 x4 or Gen4 x4/Gen4 x4/Gen4 x4/Gen4 x4||RP/BP||x16, x8, x4_0, x4_1|
|Configuration Mode 3||Gen3 x8 or Gen4 x8||EP||x16|
In Configuration Mode 0, only the x16 core is active, and it operates in 1x16 Hard IP mode (in either Gen3 or Gen4).
In Configuration Mode 2, all four cores (x16, x8, x4_0, x4_1) are active, and they operate as four Gen3 x4 cores or four Gen4 x4 cores.
In Configuration Mode 3, the x16 core is active, and it operates in 1x8 Hard IP mode (in either Gen3 or Gen4).
Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes. For more details, refer to the Overview section of the Interfaces chapter.