4.4.3. Avalon® -ST RX Interface rx_st_ready Behavior
The following timing diagram illustrates the timing of the RX interface when the application throttles the P-Tile IP for PCIe by deasserting rx_st_ready_i. The Transaction Layer in the P-Tile IP deasserts rx_st_valid_o within 27 cycles of the rx_st_ready_i deassertion. This behavior means that the readyAllowance of this interface is 27 (readyAllowance defines the relationship between the deassertion of the ready signal and the deassertion of the valid signal). It also reasserts rx_st_valid_o within 27 cycles after rx_st_ready_i reasserts if there is more data to send. This behavior means that the readyLatency of this interface is 27 (readyLatency defines the relationship between the assertion of a ready signal and the assertion of a valid signal). rx_st_data_o is held until the application is able to accept it.