DisplayPort Intel® Arria 10 FPGA IP Design Example User Guide

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ID 683050
Date 11/12/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices 4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives 5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Arria® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Arria® 10 DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Creating RX-Only or TX-Only Designs 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameters 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.4.5. View the Results x
3.4.5.1. LED Functions
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Arria® 10 Devices
4. DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide Archives
5. Revision History for DisplayPort Intel® Arria® 10 FPGA IP Design Example User Guide

2.5. Design Components

The DisplayPort Intel® FPGA IP design example requires these components.
Table 11.  Core System Components
Module Description
Core System (Platform Designer)

The core system consists of the Nios II Processor and its necessary components, DisplayPort RX and TX core sub-systems.

This system provides the infrastructure to interconnect the Nios II processor with the DisplayPort Intel® FPGA IP (RX and TX instances) through Avalon memory-mapped (Avalon-MM) interface within a single Platform Designer system to ease the software build flow.

This system consists of:
  • CPU Sub-System
  • RX Sub-System
  • TX Sub-System
RX Sub-System (Platform Designer)
The RX sub-system consists of:
  • Clock Source—The clock source to the DisplayPort RX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
  • DisplayPort RX Core—DisplayPort Sink IP core, VESA DisplayPort Standard version 1.4.
  • Debug FIFO—This FIFO captures all DisplayPort RX auxiliary cycles, and prints out in the Nios II Debug terminal.
  • PIO—The parallel IO that triggers the MSA capture, and prints out when the on-board push button (PB) is pressed.
  • Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon-MM interface between components within the RX sub-system to the Nios II processor in the Core sub-system.
  • EDID—The EDID RAM is only used to store the desired EDID value in the RAM and connect to the DisplayPort Sink IP core. This component is only used when you disable the Enable GPU Control option in the RX core.
TX Sub-System (Platform Designer)
The TX sub-system consists of:
  • Clock Source—The clock source to the DisplayPort TX core. This sub-system has two clock sources integrated: 100 MHz and 16 MHz.
  • Reset Bridge—The bridge that connects the external signal to the sub-system. This bridge synchronizes to the respective clock source before it is used.
  • DisplayPort TX Core—DisplayPort Source IP core, VESA DisplayPort Standard version 1.4.
  • Debug FIFO—This FIFO captures all DisplayPort TX auxiliary cycles, and prints out in the Nios II Debug terminal. This component is only used when the TX_AUX_DEBUG parameter is turned on.
  • PIO—The parallel IO that triggers the DPTX register update in software (tx_utils.c).
  • Avalon-MM Pipeline Bridge—This Avalon-MM bridge interconnects the Avalon-MM interface between components within the TX sub-system to the Nios II processor in the Core sub-system.
Table 12.  DisplayPort RX PHY Top and TX PHY Top Components
Module Description
RX PHY Top
The RX PHY top level consists of the components related to the receiver PHY layer.
  • Transceiver Native PHY (RX)—The transceiver block that receives the serial data from an external video source and deserializes it to 20-bit or 40-bit parallel data to the DisplayPort sink IP core. This block supports up to 8.1 Gbps (HBR3) data rate with 4 channels.
  • Transceiver PHY Reset Controller—The RX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing.
  • RX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY block to receive serial data in the supported data rates (RBR, HBR, HBR2, and HBR3).
Note: 8.1 Gbps is available only in the Intel® Quartus® Prime Pro Edition software.
TX PHY Top
The TX PHY top level consists of the components related to the transmitter PHY layer.
  • Transceiver Native PHY (TX)—The transceiver block that receives 20-bit or 40-bit parallel data from the DisplayPort Intel® FPGA IP and serializes the data before transmitting it. This block supports up to 8.1 Gbps (HBR3) data rate with 4 channels.
    Note: You must set the TX channel bonding mode to PMA and PCS bonding and the PCS TX Channel bonding master parameter to 0 (default is auto).
  • Transceiver PHY Reset Controller—The TX Reconfiguration Management module triggers the reset input of this controller to generate the corresponding analog and digital reset signals to the Transceiver Native PHY block according to the reset sequencing.
  • TX Reconfiguration Management—This block reconfigures and recalibrates the Transceiver Native PHY and TX PLL blocks to transmit serial data in the required data rates (RBR, HBR, HBR2, and HBR3).
  • TX PLL—The transmitter PLL block provides a fast serial fast clock to the Transceiver Native PHY block. For the DisplayPort Intel® FPGA IP design example, Intel® uses transmitter fractional PLL (FPLL).
Note: 8.1 Gbps is available only in the Intel® Quartus® Prime Pro Edition software.
Table 13.  Loopback Top Component
Module Description
Pixel Clock Recovery (PCR)

This module recovers pixel clock (derived from the DisplayPort Sink MSA information). PCR dynamically detects the received video format and recovers the corresponding pixel clock.

This module also integrates a DCFIFO as video data buffer from the receiver and transmitter clock domains. This module supports resolutions up to 8Kp30 only.

Note: Your design may not require PCR if you use your own recovery logic or any of the Video and Image Processing (VIP) IP cores.
Table 14.  Top-Level Common Blocks
Module Description
Transceiver Arbiter

This generic functional block prevents transceivers from recalibrating simultaneously when either RX or TX transceivers within the same physical channel require reconfiguration. The simultaneous recalibration impacts applications where RX and TX transceivers within the same channel are assigned to independent IP implementations.

This transceiver arbiter is an extension to the resolution recommended for merging simplex TX and simplex RX into the same physical channel. This transceiver arbiter also assists in merging and arbitrating the Avalon-MM RX and TX reconfiguration requests targeting simplex RX and TX transceivers within a channel as the reconfiguration interface port of the transceivers can only be accessed sequentially. The transceiver arbiter is not required when only either RX or TX transceiver is used in a channel.

The transceiver arbiter identifies the requester of a reconfiguration through its Avalon-MM reconfiguration interfaces and ensures that the corresponding tx_reconfig_cal_busy or rx_reconfig_cal_busy is gated accordingly.

IOPLL

IOPLL generates common source clock: dp_rx_vid_clkout and clk_16 (16 MHz) for the DisplayPort system.

  • dp_rx_vid_clkout—used as RX core video clock of the video data stream and PCR video input clock.
  • clk_16—Used as DisplayPort auxiliary clock and PCR reference clock.
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