Ethernet Design Example Components User Guide

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ID 683044
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

2.5. Interface Signals

Figure 6. Interface Signals of TOD Synchronizer
Table 23.  Signals Description
Name Direction Width Description
Clock and Reset Signals
clk_master In 1 Master TOD clock domain.
reset_master In 1 Synchronous reset signal in the master TOD clock domain.
clk_slave In 1 Slave TOD clock domain.
reset_slave In 1 Synchronous reset signal in the slave TOD clock domain.
clk_sampling In 1 Sampling clock to measure the transfer latency.

Not available for SYNC_MODE = 18.

Interface Signals
start_tod_sync In 1 Assert this signal to start the synchronization process. Synchronization continues as long as this signal is asserted.
tod_master_data[] In 64 or 96 Carries the 64-bit or 96-bit time of day from the master TOD clock. The width of this signal is determined by the TOD_MODE parameter
tod_slave_valid Out 1 When asserted, the signal indicates that the data on the tod_data_slave bus is valid and ready for transfer in the following cycle. This signal stays asserted for only 1 clock cycle.
tod_slave_data[] Out 64 or 96 Carries the 64-bit or 96-bit time of day for the slave TOD clock. This time of day is synchronized to the master TOD clock with an additional one clock cycle because it takes one clock cycle to transfer the time of day to the slave TOD clock.

The width of this signal is determined by the TOD_MODE parameter.

Level Two Title