Ethernet Design Example Components User Guide

ID 683044
Date 3/28/2022
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1.5.4. Clocking Requirements

  • Expect the clk frequency to be equal or less than 100 MHz.
  • The period_clk must have the same clock source as the timestamping consumer, e.g. MAC. In case the frequency exceeds 156.25 MHz, when OFFSET_JITTER_WANDER_EN is enabled, use the ToD in conjunction with the TOD Synchronizer.
  • For advanced accuracy Pulse per Second feature, IOPLL instantiation is required and must meet the following clocking requirements:
    • The IOPLL reference clock must be driven by TOD period clock or any clock with zero ppm difference from TOD period clock.
    • The IOPLL scan clock must be the same clock connecting to iopll_scan_clk. Set the iopll_scan_clk with any value between 50MHz and 100 MHz. The lower the frequency of the iopll_scan_clk, the longer the IOPLL takes to carry out the phase shift operation.
    • Set the pps_sampling_clk frequency as close as possible to the formula given in the interface description per Table 12. Deviation from the formula can affect the accuracy of the PPS signal. However, a few MHz difference is acceptable and still gives an accuracy within 2ns range.