Ethernet Design Example Components User Guide

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ID 683044
Date 3/28/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Time-of-day Clock 2. Time-of-day Synchronizer 3. Packet Classifier 4. Ethernet Design Example Components User Guide Archives 5. Document Revision History for the Ethernet Design Example Components User Guide
1. Time-of-day Clock x
1.1. Release Information 1.2. Resource Utilization 1.3. Configuring the TOD Clock 1.4. Using the TOD Clock 1.5. Interface Signals 1.6. Configuration Registers
1.1. Release Information x
1.1.1. Pulse Per Second Device Speed Grade Support
1.4. Using the TOD Clock x
1.4.1. Adjusting TOD Drift 1.4.2. Adjusting Offset, Jitter, and Wander 1.4.3. Correcting TOD Offset 1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode) x
1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface 1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP
1.5. Interface Signals x
1.5.1. Avalon Memory-Mapped Signals 1.5.2. Time-of-day Signals 1.5.3. Pulse-Per-Second Signals 1.5.4. Clocking Requirements
2. Time-of-day Synchronizer x
2.1. Release Information 2.2. Resource Utilization 2.3. Configuring the TOD Synchronizer 2.4. Using the TOD Synchronizer 2.5. Interface Signals
2.4. Using the TOD Synchronizer x
2.4.1. Sampling Clock Frequency
3. Packet Classifier x
3.1. Release Information 3.2. Resource Utilization 3.3. Configuring the Packet Classifier 3.4. Interface Signals
3.4. Interface Signals x
3.4.1. Clock and Reset Signals 3.4.2. Avalon® Streaming Interface Signals 3.4.3. Control Signals
1. Time-of-day Clock
2. Time-of-day Synchronizer
3. Packet Classifier
4. Ethernet Design Example Components User Guide Archives
5. Document Revision History for the Ethernet Design Example Components User Guide

1.4.2. Adjusting Offset, Jitter, and Wander

The TOD clock supports several types of adjustments:
  • Offset—use the OffsetNS and OffsetFNS registers to adjust large offsets in assisting faster system convergence. The offset can be positive or negative. The maximum correction is (109 - 50) ns.
  • Jitter—use the JitterTimer and JitterAdjust registers to achieve small time scales (milliseconds or microseconds) frequency correction.

    The jitter adjustment can either be a positive or negative adjustment per unit time. This helps achieve better frequency corrections. For very low values of the jitter, such as 1 ns correction for every second, the timer must be larger and the adjustment value must be smaller.

    For example, to achieve 1 ns correction every second in a clock domain of 3.2 ns period, configure the registers as follow:
    • JitterTimer = 0x12A05F20, which is the hexadecimal value of (1000000000/3.2).
    • JitterAdjust = 0x10000, which sets the nanosecond field to 0x1 and the fractional nanosecond field to 0x0.
  • Wander—use the WanderTimeLSB, WanderTimeMSB, and WanderAdjust registers to achieve large time scale correction.

    The wander adjustment can either be a positive or negative adjustment per unit time. Wander adjustments are typically on larger time scales such as per hour. For very low values of the wander such as 1 ns per 24 hours, the timer must be larger and the adjustment value must be smaller.

    For example, to achieve 1 ns correction every 24 hours in a clock domain of 3.2 ns period, configure the registers as follow:
    • WanderTimerLSB[29:0] = 0x2D68_B000
    • WanderTimerMSB[15:0] = 0x6239
Note: The adjustments are available only when PERIOD_CLOCK_FREQUENCY is set to 0.
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