Ethernet Design Example Components User Guide

ID 683044
Date 12/13/2021

A newer version of this document is available. Customers should click here to go to the newest version.

3.3. Configuring the Packet Classifier

In the Intel® Quartus® Prime software, instantiate the Packet Classifier by selecting Ethernet Packet Classifier Intel® FPGA IP from the IP Catalog or Platform Designer (Interface Protocols > Ethernet > Reference Design Components). Specify the parameters in the following table.

Table 26.  Packet Classifier Parameters Description
Name Value Default Description
TSTAMP_FP_WIDTH 1 – 32 4 The width of the timestamp fingerprint.
SYMBOLSPERBEAT 1, 4, or 8 8 The number of symbols transferred in a clock cycle.
BITSPERSYMBOL 8 8 The number of bits per symbol transferred in a clock cycle.