Ethernet Design Example Components User Guide

ID 683044
Date 12/13/2021

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2.4. Using the TOD Synchronizer

Figure 3. TOD Synchronizer in a Design (SYNC_MODE 0 to 15)
Figure 4. TOD Synchronizer in a Design (SYNC_MODE 18)

The TOD synchronizer with SYNC_MODE = 0 to 15 uses a dual-clock FIFO buffer to receive the time of day from the master TOD clock and transmits it to the slave TOD clock. To ensure that the synchronization is accurate, the transfer latency must be taken into consideration. The sampling clock (clk_sampling) samples the fill level of the FIFO buffer and calculates the latency. Derive this clock signal from the same source as the master TOD clock or the slave TOD clock using a PLL.

The sampling clock (clk_sampling) is not required for TOD synchronizer with SYNC_MODE = 18 as it uses a different technique for synchronization.