1.6.1. Generating Programming Files for HPS Boot First Boot Flows
In HPS Boot First boot flows, the HPS I/O and EMIF are configured and the HPS is booted before configuring the FPGA I/O and core.
Configuring the HPS I/O for the first time and then loading the HPS FSBL is called "Phase 1 configuration". The subsequent configuration of FPGA I/O and core by HPS is called "Phase 2 configuration".
To generate programming files for HPS Boot First boot flows:
- Generate the primary programming files for your design, as Generating Primary Device Programming Files describes.
- Click File > Programming File Generator.
- For Device family, select your target device. The options available in the Programming File Generator change dynamically, according to your device and configuration mode selection.
- For Configuration mode, select an Active Serial mode that your device supports. Configuration Modes (Programming File Generator) describes all modes.
- On the Output Files tab, select Raw Binary File for HPS Core Configuration (.rbf), then select the following files:
JTAG Indirect Configuration File for Periphery Configuration (.jic)
Raw Programming Data File (.rpd)
Secondary Programming Files (Programming File Generator) describes all output files.
- On the Output Files tab, select Raw Programming Data File (.rpd) and click Edit.
- Optional: Optional: In the RPD Properties dialog box, set Bit swap to On.
Important: This step may or may not be required, depending on the external programmer that you use.
- Specify the Output directory and Name for the file you generate. Output Files Tab Settings (Programming File Generator) describes all options.
- On the Input Files tab, click Add Bitstream to add your .sof file or files.
- For each .sof file that you add, edit their properties as follows:
- Select the .sof file and click Properties.
- In the Bootloader field of Input File Properties dialog box, add the U-Boot First State Boot Loader (FSBL) file. Ensure that the file is an Intel-format hexadecimal (.hex) file.
- To add other data, such as U-Boot Second Stage Boot Loader (SSBL) file or Phase 2 bitstreams:
- Click Add Raw Data and specify an Intel-format hexadecimal (.hex) file.
- Select the file you added and click Properties.
- In the Input File Properties dialog box, set the Bit swap field to On.
Your Phase 1 and Phase 2 bitstreams are subject to the following restrictions:
- Your Phase 1 and Phase 2 bitstreams must be generated by the same version of Intel® Quartus® Prime, including any applied patches or updates.
- If your Phase 1 and Phase 2 bitstreams are generated from different Intel® Quartus® Prime Pro Edition projects, review the following Knowledge Base article for additional steps that might be required:
- To specify the .sof file that occupies the flash memory partition, click Add Partition on the Configuration Device tab. Add Partition Dialog Box (Programming File Generator) describes all options.
Figure 22. Add Flash Partition
- To select a supported flash memory device and predefined programming flow, click Add Device on the Configuration Device tab. Alternatively, click <<new device>> to define a new flash memory device and programming flow. Configuration Device Tab Settings describes all settings.
- Click the Select button for Flash Loader and select the device that controls loading of the flash memory device. Select Devices (Flash Loader) Dialog Box describes all settings.
- After you specify all options in Programming File Generator, the Generate button enables. Click Generate to create the files.
- Optional: Export your settings to PFG setting file (.pfg) so that you can use these settings again with the quartus_pfg command line tool.
For details, refer to quartus_pfg Command Line Tool.