50G Interlaken Design Example User Guide

ID 683029
Date 10/31/2022

1.4. Simulating the Design

Figure 6. Procedure
Follow these steps to simulate the testbench:
  1. Change to the testbench simulation directory <example_design_install_dir>/example_design_a10/testbench.
  2. Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete. Refer to the table Steps to Run Simulation.
  3. Analyze the results.
    Table 1.  Steps to Run Simulation
    Simulator Instructions
    ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type
    vsim -do vlog_pro.do
    If you prefer to simulate without bringing up the GUI, type
    vsim -c -do vlog_pro.do
    VCS* In the command line, type sh vcstest.sh
    Xcelium* In the command line, type sh xcelium.sh
A successful simulation ends with the following message: