50G Interlaken Design Example User Guide

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ID 683029
Date 10/31/2022
Public

2.5. Interface Signals

Table 2.  Arria 10 50G Interlaken IP Core Hardware Example Design Signals

Port Name

Direction

Width (Bits)

Description

clk50

Input

1

System clock input. Clock frequency must be 50 MHz.

pll_ref_clk

Input

1

Transceiver reference clock. Drives the RX CDR PLL.

rx_pin

Input

Number of lanes

Receiver SERDES data pin.

tx_pin

Output

Number of lanes

Transmit SERDES data pin.

sys_pll_reset_n Input 1 System reset.
Level Two Title