1.4. Simulating the Design
Figure 6. ProcedureFollow these steps to simulate the testbench:
- Change to the testbench simulation directory <example_design_install_dir>/example_design_a10/testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Your script should check that the SOP and EOP counts match after simulation is complete. Refer to the table Steps to Run Simulation.
- Analyze the results.
Table 1. Steps to Run Simulation Simulator Instructions ModelSim* SE or Questa* or Questa*-Intel® FPGA Edition In the command line, type
vsim -do vlog_pro.doIf you prefer to simulate without bringing up the GUI, type
vsim -c -do vlog_pro.do
VCS* In the command line, type sh vcstest.sh
A successful simulation ends with the following message: