2.6. Register Map
Offset | Name | Access | Description |
---|---|---|---|
8'h00 | Reserved | ||
8'h01 | Reserved | ||
8'h02 | System PLL reset | RO | Following bits indicates system PLL reset request and enable value:
|
8'h03 | RX lane aligned | RO | Indicates the RX lane alignment. |
8'h04 | WORD locked | RO | [NUM_LANES–1:0] – Word (block) boundaries identification. |
8'h05 | Sync locked | RO | [NUM_LANES–1:0] – Metaframe synchronization. |
8'h06 - 8'h09 | CRC32 error count | RO | Indicates the CRC32 error count. |
8'h0A | CRC24 error count | RO | Indicates the CRC24 error count. |
8'h0B | Overflow/Underflow signal | RO | Following bits indicate:
|
8'h0C | SOP count | RO | Indicates the number of SOP. |
8'h0D | EOP count | RO | Indicates the number of EOP |
8'h0E | Error count | RO | Indicates the number of following errors:
|
8'h0F | send_data_mm_clk | RW | Write 1 to enable the generator signal. |
8'h10 | Reserved | ||
8'h11 | System PLL lock | RO | PLL lock indication. |
Note:
- Example design register address starts with 0x20** while the 50G Interlaken core register address starts with 0x10**.
- Access code: RO—Read Only, and RW—Read/Write.
- System console reads the example design registers and reports the test status on the screen.