Intel® oneAPI DPC++/C++ Compiler Developer Guide and Reference

ID 767253
Date 3/31/2023
Public

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Document Table of Contents

m, Qm

Tells the compiler which features it may target, including which instruction set architecture (ISA) it may generate.

Syntax

Linux:

-mcode

Windows:

/Qmcode

Arguments

code

Indicates to the compiler a feature set that it may target, including which instruction sets it may generate. Many of the following descriptions refer to Intel® Streaming SIMD Extensions (Intel® SSE) and Supplemental Streaming SIMD Extensions (SSSE). Possible values are:

avx

May generate Intel® Advanced Vector Extensions (Intel® AVX), SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

sse4.2

May generate Intel® SSE4.2, SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

sse4.1

May generate Intel® SSE4.1, SSE3, SSE2, SSE, and SSSE3 instructions.

ssse3

May generate SSSE3 instructions and Intel® SSE3, SSE2, and SSE instructions.

sse3

May generate Intel® SSE3, SSE2, and SSE instructions.

sse2

May generate Intel® SSE2 and SSE instructions.

This compiler option also supports many of the -m option settings available with gcc. For more information on gcc settings for -m, see the gcc documentation.

Default

varies

If option arch is not specified, the default target architecture supports Intel® SSE2 instructions.

Description

This option tells the compiler which features it may target, including which instruction sets it may generate.

Code generated with these options should execute on any compatible, non-Intel processor with support for the corresponding instruction set.

For compatibility with gcc, the compiler allows the following options but they have no effect. You will get a warning error, but the instructions associated with the name will not be generated. You should use the suggested replacement options.

gcc Compatibility Option

Suggested Replacement Option

-mfma

-march=core-avx2

-mbmi, -mavx2, -mlzcnt

-march=core-avx2

-mmovbe

-march=atom -minstruction=movbe

-mcrc32, -maes, -mpclmul, -mpopcnt

-march=corei7

-mvzeroupper

-march=corei7-avx

-mfsgsbase, -mrdrnd, -mf16c

-march=core-avx-i

NOTE:

This option only applies to host compilation. When offloading is enabled, it does not impact device-specific compilation.

IDE Equivalent

None

Alternate Options

None

See Also