Visible to Intel only — GUID: GUID-C9900300-457A-4D77-9120-21ACA55345F7
Visible to Intel only — GUID: GUID-C9900300-457A-4D77-9120-21ACA55345F7
advisor Command Option Reference
The advisor command currently supports the options shown below.
Option |
Description |
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Set an accuracy level for the Offload Modeling collection preset. |
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Add loops (by file and line number) to the loops selected for deeper analysis. |
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Specify the directory where the target application runs during analysis, if it is different from the current working directory. |
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Assume that a loop has dependencies if the loop dependency type is unknown. |
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Estimate invocation taxes assuming the invocation tax is paid only for the first kernel launch. |
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When searching for an optimal N-dimensional offload, assume there are dependencies between inner and outer loops. |
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Assume data is only transferred once for each offload, and all instances share that data. |
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Finalize Survey and Trip Counts & FLOP analysis data after collection is complete. |
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Emulate the execution of more than one instance simultaneously for a top-level offload. |
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Run benchmarks on only one concurrently executing Intel Advisor instance to avoid concurrency issues with regard to platform limits. |
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Generate a Survey report in bottom-up view. |
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Enable binary visibility in a read-only snapshot you can view any time. |
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Select what binary files will be added to a read-only snapshot. |
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Set the cache hierarchy to collect modeling data for CPU cache behavior during Trip Counts & FLOP analysis. |
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Simulate device cache behavior for your application. |
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Enable source code visibility in a read-only snapshot you can view any time (with the --snapshot action). Enable keeping source code cache within a project (with the --collect action). |
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Enable cache simulation for Performance Modeling. |
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Set the cache associativity for modeling CPU cache behavior during the Memory Access Patterns analysis. |
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Set the cache line size (in bytes) for modeling CPU cache behavior during Memory Access Patterns analysis. |
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Set the focus for modeling CPU cache behavior during Memory Access Patterns analysis. |
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Specify what percentage of total memory accesses should be processed during cache simulation. |
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Set the cache set size (in bytes) for modeling CPU cache behavior during Memory Access Patterns analysis. |
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Check the profitability of offload regions and add only profitable regions to a report. |
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Clear all loops previously selected for deeper analysis. |
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Specify a device configuration to model your application performance for. |
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Use the projection of x86 logical instructions to GPU logical instructions. |
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Project x86 memory instructions to GPU SEND/SENDS instructions. |
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Count the number of accesses to memory objects created by code regions. |
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Project x86 MOV instructions to GPU MOV instructions. |
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Select how to model SEND instruction latency. |
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Specify a scale factor to approximate a host CPU that is faster than the baseline CPU by this factor. |
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Set the delimiter for a report in CSV format. |
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Specify the ablosute path or name for a custom TOML configuration file with additional modeling parameters. |
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Limit the maximum amount (in MB) of raw data collected during Survey analysis. |
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Analyze potential data reuse between code regions. |
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Set the level of details for modeling data transfers during Characterization. |
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Estimate data transfers in details and latencies for each transferred object. |
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Specify memory page size to set the traffic measurement granularity for the data transfer simulator. |
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Show only floating-point data, only integer data, or data for the sum of both data types in a Roofline interactive HTML report. |
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Remove previously collected trip counts data when re-running a Survey analysis with changed binaries. |
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Do not account for optimized traffic for transcendentals on a GPU. |
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