Types of DPC++ FPGA Compilation
Device Image Type
Time to Compile
The FPGA device code is compiled to the CPU. Use the Intel® FPGA Emulation Platform for OpenCL™ software to verify your SYCL code's functional correctness.
The FPGA device code is compiled to the CPU. Use the Questa*-Intel® FPGA Edition simulator to debug your code.
The FPGA device code is partially compiled for hardware. The compiler generates an optimization report that describes the structures generated on the FPGA, identifies performance bottlenecks, and estimates resource utilization.
FPGA Hardware Image
Generates the real FPGA bitstream to execute on the target FPGA platform.
- Performance is not representativeNever draw inferences about FPGA performance from the FPGA emulator. The FPGA emulator's timing behavior is not correlated to that of the physical FPGA hardware. For example, an optimization that yields a 100x performance improvement on the FPGA may show no impact on the emulator performance. The emulator might show an unrelated increase or decrease.
- Undefined behavior may differIf your code produces different results when compiled for the FPGA emulator versus FPGA hardware, your code most likely exercises undefined behavior. By definition, undefined behavior is not specified by the language specification, and might manifest differently on different targets.
FPGA Optimization Report
Optimization Report Information
FPGA early image
(Compilation takes minutes to complete)
The SYCL device code is optimized and converted into an FPGA design specified in the Verilog Register-Transfer Level (RTL) (a low-level, native entry language for FPGAs). The intermediate compilation result is the FPGA early device image that is not an executable.
The optimization report generated at this stage is sometimes referred to as the
Contains significant information about how the compiler has transformed your SYCL device code into an FPGA design. The report contains the following information:
For information about the FPGA optimization report, refer to the Intel® oneAPI DPC++ FPGA Optimization Guide.
FPGA hardware image
(Compilation takes hours to complete)
The Verilog RTL specifying the design's circuit topology is mapped onto the FPGA's primitive hardware resources by the Intel® Quartus® Prime Software. The Intel® Quartus® Prime Software is included in the Intel® FPGA Add-On for oneAPI Base Toolkit, which is required for this compilation stage. The result is an FPGA hardware binary (also referred to as a bitstream).
Contains precise information about resource utilization and f
maxnumbers. For detailed information about how to analyze reports, refer to Analyze your Design section in the
Intel® oneAPI DPC++ FPGA Optimization Guide.
For information about the FPGA hardware image, refer to the Intel® oneAPI DPC++ FPGA Optimization Guide.