AN 1002: Sharing Platform Designer Packaged Subsystems

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ID 786899
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. About This Application Note 3. Packaged Subsystems Overview 4. Packaged Subsystem Author Flow 5. Packaged Subsystem User Flow 6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems
2. About This Application Note x
2.1. Document Prerequisites
3. Packaged Subsystems Overview x
3.1. User Personas for Packaged Subsystems 3.2. Terminology for Packaged Subsystems
4. Packaged Subsystem Author Flow x
4.1. Step 1: Create a Project and Platform Designer System 4.2. Step 2: Add Components to the System 4.3. Step 3: Connect Components in the System 4.4. Step 4: Create and Configure a Packaged Subsystem 4.5. Step 5: Revise a Packaged Subsystem
4.4. Step 4: Create and Configure a Packaged Subsystem x
4.4.1. Editing the Packaged Subsystem 4.4.2. Step 4a: Add Two Checkbox Controls 4.4.3. Step 4b: Enable or Disable Modules and Checkboxes 4.4.4. Step 4c: Run run_system_script 4.4.5. Step 4d: Iterate Over All Parameters 4.4.6. Step 4e: Setting DisplayPort IP Functionality 4.4.7. Step 4f: Make Packaged Subsystem Unlockable 4.4.8. Step 4g: Sync System Infos, Assign Base Addresses, and Save
5. Packaged Subsystem User Flow x
5.1. Step 1: Create the User Project and System 5.2. Step 2: Add Components to the User System 5.3. Step 3: Instantiate the Packaged Subsystem 5.4. Step 4: Unlock the Packaged Subsystem 5.5. Step 5: Integrate the Top Hierarchy of the System 5.6. Step 6: Generate HDL and Run Synthesis
1. Answers to Top FAQs
2. About This Application Note
3. Packaged Subsystems Overview
4. Packaged Subsystem Author Flow
5. Packaged Subsystem User Flow
6. Document Revision History of AN 1002: Sharing Platform Designer Packaged Subsystems

5.2. Step 2: Add Components to the User System

After creating the packaged subscript user system, follow these steps to add Intel FPGA IP components from the IP Catalog to the system.

  1. From Platform Designer's IP Catalog, instantiate the following components into the system. Keep the defaults for all other parameters.
    Table 4.  User System Subsystem IP Parameters and Module Names
    Intel FPGA IP Parameters To Specify HDL Entity Name
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edges—deassert
    		cpu_reset_bridge
    Clock Bridge Intel FPGA IP Explicit clock rate—100000000 Hz mgmt_clk
    On-Chip Memory Intel FPGA IP Total memory size—285696 bytes onchip_mem
    JTAG UART Intel FPGA IP Write FIFO Buffer Depth—1024 jtag_uart
    Interval Timer Intel FPGA IP Units—us sys_clock_timer
    Avalon I2C Intel FPGA IP Depth of Fifo—32 i2c_master
    System ID Peripheral Intel FPGA IP N/A sysid
    Nios V/m Microcontroller Intel FPGA IP1 Turn on Enable Reset from Debug Modules cpu
    Clock Bridge Intel FPGA IP Explicit clock rate—16000000 Hz dp_rx_clk_16
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edges—None
    		dp_rx_reset_bridge
    Clock Bridge Intel FPGA IP Explicit clock rate—16000000 Hz dp_tx_clk_16
    Reset Bridge Intel FPGA IP
    • Active low reset—Enable
    • Synchronous edges—None
    		dp_tx_reset_bridge
  2. Click File > Save to save the system. You can ignore any errors or warnings about the system at this point.
Figure 25. user_system Components in the System View Tab


1 This configuration is for demonstration purposes only, as actually BSP generation is not possible for designs with a Nios V/m or Nios II processor connected to a peripheral in a packaged subsystem.
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