Verilog Reload Coefficients for FIR Compiler



This design example demonstrates how to reload coefficients from a file when using the finite impulse response (FIR) Compiler IP MegaCore function. FIR Compiler provides the flexibility to change the coefficients at run time. While the FIR Compiler is processing the data with one set of coefficients, you can reload another set without halting core processing.

To optimize silicon efficiency, coefficients are not stored in their natural order. This example explains the steps for reordering the coefficients using the precompiled executable coef_seq.exe. The filter uses four sets of coefficients: low pass, high pass, band pass, and band reject filters. The first two are parameterized in the IP Toolbench; the latter two must be reloaded at run time and require reordering in advance. The provided testbench shows you how to set up controls to reload the coefficients to meet the timing requirements.

Download the files used in this example:

The use of this design is governed by, and subject to, the terms and conditions of the Intel® Design Example License Agreement.

Files in the zip download include:

  • fir91.v - FIR compiler wrapper file
  • coef_reload_tb.v - Testbench file
  • coef_reload_msim.tcl - Tcl script for running a functional simulation using the ModelSim* tool
  • coef_seq.exe - Windows executable that reorders the coefficients

Figure 1. FIR compiler port listing.