Article ID: 000092061 Content Type: Troubleshooting Last Reviewed: 08/24/2022

Why there is no video output seen after programming the SDI II Intel® FPGA IP multi-rate or triple-rate design with the Intel® Agilex™ F-tile device using the Intel® Quartus® Prime Pro Edition Software Programmer v22.2?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software Programmer version 22.2, no SDI II video output is displayed on the receiver side when using the SDI II Intel® FPGA IP multi-rate or triple-rate designs on the Intel® Agilex™ F-tile devices. This is due to the rx_ready signal not being asserted after performing dynamic reconfiguration of the F-Tile PHY transceiver.

    This issue impacts all SDI II Intel® FPGA IP design examples that support dynamic reconfiguration. 

     

     

    Resolution

    A patch is available to fix this problem for the Intel® Quartus® Prime Pro Edition Software Programmer version 22.2. 

    Download and install Patch 0.06 from the following links:

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

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