Article ID: 000090518 Content Type: Troubleshooting Last Reviewed: 01/11/2023

Why there is no video output seen after programming the SDI II Intel® FPGA IP multi-rate or triple-rate design with the Intel® Agilex™ F-tile device using the Intel® Quartus® Prime Pro Edition Software Programmer v22.1?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Interfaces
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition Software Programmer version 22.1, no SDI II video output is displayed on the receiver side when using the SDI II Intel® FPGA IP multi-rate or triple-rate designs on the Intel® Agilex™ F-tile devices. This is due to the rx_ready signal not being asserted after performing dynamic reconfiguration of the F-Tile PHY transceiver.

     

    This issue impacts all SDI II Intel® FPGA IP design examples that support dynamic reconfiguration. 

    Resolution

    To work around this issue, use the Intel® Quartus® Prime Pro Edition Software Programmer version 21.4 (stand-alone software) to download the .sof file generated from the Intel® Quartus® Prime Pro Edition Software version 22.1.

     

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Agilex™ 7 FPGAs and SoC FPGAs

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