Why does the SDI II Intel® FPGA IP Multi-rate (up to 12G-SDI) design fail to work when merging both TX and RX simplex mode in the same channel with the Intel Agilex® 7 device?

Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 with patch 0.06 installed, the F-tile SDI II Intel® FPGA IP Multi-rate (up to 12G-SDI) design will fail to work when merging both TX and RX simplex mode in the same channel.

This issue does not impact the HD-SDI, 3G-SDI, and Triple rate (up to 3G-SDI) designs with both TX and RX simplex mode in the same channel.

To work around this problem, the TX and RX lanes must be separated into two different channels when using TX and RX simplex mode in Multi rate designs.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.