Article ID: 000085042 Content Type: Error Messages Last Reviewed: 08/27/2013

Warning (12010): Port "rx_cda_reset" on the entity instantiation of "ALTLVDS_RX_component" is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>. The extra bits will be driven by GND.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The ALTLVDS_RX megafunction in the Quartus® II software version 10.0 does not correctly create the required number of input ports for rx_cda_reset.  This port should have a width equal to the number of channels.

    Resolution

    To work around this problem open the HDL variation file of the ALTLVDS_RX megafunction in your design and manually edit the port width of rx_cda_reset.

    The port width should follow the format of [number_of_channels-1:0].

    This problem is fixed in the Quartus II software version 10.0SP1.

    Related Products

    This article applies to 5 products

    Stratix® IV E FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® III FPGAs
    Arria® II GX FPGA

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