Article ID: 000078921 Content Type: Troubleshooting Last Reviewed: 08/27/2013

The ALTLVDS_RX megafunction in the Quartus® II software version 10.0 does not correctly create the required number of output ports for rx_dpa_locked. This port should have a width equal to the number of channels.

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The ALTLVDS_RX megafunction in the Quartus® II software version 10.0 does not correctly create the required number of output ports for rx_dpa_locked.  This port should have a width equal to the number of channels.

    To work around this problem open the HDL variation file of the ALTLVDS_RX megafunction in your design and manually edit the port width of rx_dpa_locked and any sub_wire buses connected to rx_dpa_locked.

    The port width should follow the format of [number_of_channels-1:0].

     

    Warning Message:

    Warning (12010): Port "rx_dpa_locked" on the entity instantiation of "ALTLVDS_RX_component" is connected to a signal of width 1. The formal width of the signal in the module is <number_of_channels>.  The extra bits will be left dangling without any fan-out logic.

    Resolution This problem is fixed in the Quartus II software version 10.1.

    Related Products

    This article applies to 5 products

    Arria® II GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA
    Stratix® IV GX FPGA
    Stratix® III FPGAs