Article ID: 000082801 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there a problem with single ended input reference clock support in Stratix III and Stratix IV devices when using altlvds in Quartus II software version 9.1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Yes, there is a problem with single ended input reference clock support in Stratix® III and Stratix IV devices when using altlvds in Quartus® II software version 9.1

     

    The device datasheet shows support for both single ended and differential reference clocks in the High Speed I/O specifications. However, during compilation in Quartus II software version 9.1, the fitter overwrites the user assigned single ended clock I/O standard and creates a complement pin and converts it to the LVDS I/O standard.

     

     

    Resolution

    This is fixed in Quartus II software version 9.1SP1.

    Related Products

    This article applies to 4 products

    Stratix® IV GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA
    Stratix® III FPGAs

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