Article ID: 000080130 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do Stratix IV devices support a single ended reference clock for LVDS receivers (altlvds)?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, Stratix® IV devices support single ended reference clocks for the altlvds receiver rx_inclock port. There are two different maximum single ended reference clock frequency specifications based on the configuration of the altlvds receiver:

1) DPA and Soft-CDR mode
The specifications are same as the differential reference clock frequency specifications

2) Source synchronous (non-DPA) mode
The specifications are lower than the differential reference clock frequency specifications.

The updated specifications are available beginning in the Stratix IV Device Datasheet (PDF) version 4.0.

Related Products

This article applies to 2 products

Stratix® IV FPGAs
Stratix® IV GX FPGA

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