Article ID: 000082330 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do Stratix III devices support a single ended reference clock for LVDS receivers (altlvds)?

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Description

Yes, Stratix® III devices support single ended reference clocks for the altlvds receiver rx_inclock port only for DPA and Soft-CDR modes. The maximum single ended reference clock frequency specifications are the same as the differential reference clock specifications.

The Stratix III Device Data Sheet: DC and Switching Characteristics (PDF) will be updated in a future release to include the maximum single ended reference clock frequency specifications.

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