Timing models for Stratix® V and Arria® V devices are being updated in the the Quartus® II software version 13.0 SP1 DP5 to address issues in version 13.0 SP1.
During timing model finalization of the last 28-nm devices, Altera identified timing model miscorrelations. As part of our continuous improvement processes, Altera audited all devices and found issues affected other devices. Therefore the model changes affect devices that had been designated with "Final" timing status in previous versions of the Quartus II software.
Refer to the Workaround/Fix section below to download the software patch that includes the timing model changes, download a script to help determine if your design is affected, and get instructions on how to rerun timing analysis with an updated version of the Quartus II software.
Stratix V and Arria V GZ Model Issue: Input Pin to fPLL Reference Clock Path
If a design that targets a Stratix V or Arria V GZ device has a fractional PLL (fPLL) reference clock that is fed directly by a dedicated clock input pin, there is a miscorrelation in the input delay. This issue impacts the design behavior only if the design relies on a specified timing relationship between the reference clock input pin and fPLL output. The following timing scenarios are affected:
- output timing if a destination register feeds off-chip (without the clock also sent off-chip), such as Tco measurement or correction
- input/receive setup timing for regular or source synchronous inputs clocked by the fPLL
- timing with zero-delay buffers and external PLL compensation modes
Other clocking scenarios, such as the following, are not affected:
- source synchronous outputs, transceivers, DDR memories
- sources and destinations that use clocks from same PLL
Arria V GX and GT Model Issue: Periphery Routing Mux Paths
There are timing miscorrelations related to periphery routing multiplexer paths in Arria V GX and GT devices.
The I/O pin-to-core path is missing up to 1 ns delay and the D3 delay chain is not correctly analyzed. This issue affects only general purpose pins feeding the FPGA core directly (with no I/O register). The issue does not affect I/O registers, DDR memory, transceivers or any other paths.
Routing between core and the peripheral clock (PCLK) clock buffer is missing ~300ps delay. This issue affects core routing to horizontal and vertical PCLK input, and horizontal PCLK output to core. The issue does not affect I/O pins, transceiver TX/RX, or DPA paths to the PCLK clock buffer.
Arria V GX and GT TimeQuest Issue: Clock Polarity Timing into MLAB
The TimeQuest Timing Analyzer incorrectly analyzes the timing path in Arria V GX and GT devices when there is mixed polarity of clocks into a MLAB memory block, such as a positive-edge write address register feeding a MLAB memory with a negative-edge write clock signal. TimeQuest analyzes this connection as a full cycle transfer when it should be a half cycle.
Before downloading and installing the new software, you can download the 13_0_sp1_timing.tcl script to see if the design could be affected, as described below.
To confirm whether a design is impacted by these timing model issues, retime the design in a patched version of the Quartus II software as described below.
If the script or timing analysis with a patched Quartus II software shows timing violations, then you must close timing with the updated Quartus II version. Note that ECO changes may be used in some cases to close timing without a full recompilation.
Using the 13_0_sp1_timing.tcl Timing Script:
For the Stratix V and Arria V GT issue, the script supports the Quartus II software version 12.1 SP1 DP7 and later. The script reports whether the design\'s timing performance is impacted by the timing model issue. The script generates report panels so that you can view any new failing timing paths in the project\'s Compilation Report, in the TimeQuest Timing Analyzer folder.
For the Arria V GT and GZ issues, the script suports the Quartus II software version 13.0 SP1. If the script reports that the design could be affected by the issues, retime the design with the patched Quartus II software to confirm whether the timing performance is impacted.
To start the script, run the following command from the command prompt in the project directory for the compiled design:
quartus_sh –t 13_0_sp1_timing.tcl -project <project name> [-revision <revision name>]
Retiming in the Updated Software Version:
To obtain the Quartus II software version 13.0 SP1 DP5 that includes the timing model udpates, refer to the following Solution: How do I address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 13.0 SP1?
Retime the design with the patched version by following these steps:
- Back up the design database.
- Open the design in the current Quartus II software version and export the database. On the Project menu, click Export Database. When you are prompted, export the database to the suggested export_db directory.
- Start the Quartus II software version with the updated timing model.
- Open the project in the new version of the Quartus II software. When you are prompted whether to overwrite the older database version, click Yes, and import the database from the export_db directory.
- Run the TimeQuest Timing Analyzer on the design.
- Review the timing results. If there are new timing analysis failures, you must close timing with the new timing model.