For designs that target Stratix® V devices in the Quartus® II software version 12.1, there are some known issues with the timing delays reported by the TimeQuest timing analyzer. All Stratix V devices are affected, although only the 5SGXA5, 5SGXA7, 5SGTC5, and 5SGTC7 timing models were designated final in the Quartus II software version 12.1.
For the latest information on other timing model changes in later versions of the Quartus II software, refer to the Related Solutions section below.
TCO reported for wide data widths in M20K blocks with registered outputs in Stratix V devices may be pessimistic
TCO values reported by the TimeQuest timing analyzer may be pessimistic for Stratix V M20K blocks that are more than 16 bits wide and that have registered outputs. TCO values of output register bits 16 to 39 reported by the TimeQuest timing analyzer can be pessimistic by as much as 500 ps. TCO values for bits 0 to 15 are reported correctly.
To avoid pessimistic timing values, avoid implementing RAMs that are more than 16 bits wide. If you must use RAM blocks wider than 16 bits, do not use simple dual-port mode or ROM mode.
Timing delays from Regional Clocks to Spine Clocks for Regional Clocks 73 to 91 in Stratix V devices are incorrect
For designs that target Stratix V devices, timing delays from Regional Clocks 73-91 (located on the right center and left center of the device) to Spine Clocks, are incorrectly reported as zero. The actual delay for speed grade 3 devices at 85°C is approximately 1 ns.
Regional Clocks are listed in the TimeQuest timing analyzer as QUADRANT_CLOCK routing elements, and the Regional Clock number is identified by the numeric value in the CLKCTRL_R<number> location string of the clock control (STRATIXV_CLKBUF) node. Spine Clocks are listed as SPINE_CLOCK routing elements.
To avoid this issue, avoid using Regional Clocks 73-91 on the right center and left center of the device.
Timing paths from Stratix V DSP input ports are not analyzed in some circumstances
In designs that target Stratix V devices, if DSP outputs are registered, but the
RESULTA ports are disconnected, which is common among filters, then any paths from the DSP input port to the DSP output register are not analyzed for timing.
Stratix V hold timing for LVDS-to-core transfers in non-DPA mode is incorrect
Incorrect timing models in the Quartus II software version 12.1 might result in hardware errors for designs that have low hold time margins between LVDS in non-DPA mode and core registers. The Stratix V timing model has changed in the Quartus II software version 12.1 SP1 to update the hold time requirement for transfers from the LVDS receiver’s outputs to registers in the core.
Stratix V periphery clock (PCLK) timing is incorrect
Incorrect timing models in the Quartus II software version 12.1 might result in hardware errors for designs that have low timing margin on paths that originate or end with a register clocked by a PCLK signal. This issue affects Stratix V designs that use PCLK global resources.
To determine whether a design compiled with the Quartus II software version 12.1 is affected by these issues:
- Back up the design database.
- Open the design in the Quartus II software version 12.1, and then export the database. On the Project menu, click Export Database. When you are prompted, export the database to the suggested export_db directory.
- Start the Quartus II software version 12.1 SP1 or later.
- Open the project. When you are prompted whether to overwrite the older database version, click Yes, and import the database from the export_db directory.
- Run the TimeQuest timing analyzer on the design.
If there are timing violations, run the Fitter in the Quartus II software version 12.1 SP1 or later to close timing on the design.