Article ID: 000077058 Content Type: Product Information & Documentation Last Reviewed: 12/03/2014

How can I recalibrate the Stratix V and Arria V GZ device ATX PLLs?

Environment

  • Arria® V GZ FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Stratix® V GS FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Recalibration of the Stratix® V and Arria® V GZ device ATX PLLs is dependent upon the Quartus® II software version and ATX PLL locked state.

    Quartus II software versions 13.1.1 and earlier
    ATX Tuning Register address offset 0x0 is available in Quartus II software versions 13.1.1 and earlier. Writing to ATX Tuning Register address offset 0x0 will trigger manual recalibration but the calibration routine will not disturb the ATX PLL if it already shows a locked state.

    To recalibrate the ATX PLL in Quartus II software version 13.1.1 and earlier you can use the methods below.

    Quartus II software version 13.1.1 and earlier and the ATX PLL is already locked.

    1. Write to address offset 0x0 of the "ATX Tuning Registers."

    Quartus II software version 13.1.1 and earlier and the ATX PLL is unlocked.

    1. Write the full ATX PLL MIF file to the ATX PLL.
    2. Write to address offset 0x0 of the "ATX Tuning Register."

    Quartus II software versions 13.1.2 and later
    An extra ATX Tuning Register was added in Quartus II software version 13.1.2. To recalibrate the ATX PLL you can use the method above, or use the method detailed below.

    ATX Tuning Register address offset 0x1 is available in Quartus II software versions 13.1.2 and later. Writing to ATX Tuning Register address offset 0x1 will trigger manual recalibration regardelss of the current ATX PLL locked state.

    Requirements for successful ATX PLL calibration
    In all versions of the Quartus II software, the following requirements must be met for successfull ATX PLL calibration:

    • The ATX PLL reference clock must be present, stable, and the correct frequency.
    • The transceiver reconfiguration IP reconfig_mgmt_clk signal must be present, stable, and the correct frequency.
    • The ATX PLL must not be held in reset or powered down.
    • All transceiver PHYs clocked from the ATX PLL must be reset after recalibration.

    ATX Tuning Register address offset 0x1 will be added to a future version of the Altera® Transceiver PHY IP User Guide (PDF).

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