Article ID: 000084069 Content Type: Troubleshooting Last Reviewed: 12/10/2014

Why do I see Arria V GZ and Stratix V GX device ATX PLL performance problems at temperature extremes when configured to run at datarates of 10.5 - 12.3 Gbps?

Environment

  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Arria® V GZ FPGA
  • Stratix® V GX FPGA
  • PLL
  • Reset
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see Arria® V GZ and Stratix® V GX device ATX PLL performance problems at temperature extremes when configured to run at datarates of 10.5 - 12.3 Gbps if the ATX PLL is not properly calibrated at device start-up. A failed ATX PLL calibration can cause PLL lock or transmitter jitter problems if the device temperature is decreased or elevated close to the device's supported limits. An ATX PLL may fail to calibrate if the transceiver reset sequence is not followed at device startup.

    Resolution

    To work around this problem, you must ensure that you follow the Arria V GZ and Stratix V GX device transceiver reset sequences detailed in the respective device datasheets. Specifically:

    1. You must ensure that the reset (mgmt_rst_reset) input signal to the Transceiver Reconfiguration Controller IP is asserted high at device start-up.
    2. You must ensure that the Transceiver Reconfiguration Controller IP clock signal (mgmt_clk_clk) and transceiver reference clocks are present and stable before you de-assert the reconfiguration controller IP reset signal (mgmt_rst_reset).

    The full transceiver reset sequence for the Arria V GZ and Stratix V GX devices can be found in the respective device datasheets.

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