Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ and Stratix® V GX/GT devices?

The tx_cal_busy signal will not assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ and Stratix® V GX/GT devices.

The tx_cal_busy signal is only asserted at initial runtime calibration or if you reset the reconfiguration controller.

To determine whether the ATX PLL calibration process is complete, you can read the ATX PLL control and status register. The busy status is bit 8 of the control and status register at address offset 7'h32.

This problem is fixed starting with the V-Series Transceiver PHY IP Core User Guide version 14.1.