Article ID: 000085136 Content Type: Troubleshooting Last Reviewed: 12/02/2014

Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria V GZ, and Stratix V GX/GT devices?

Environment

  • Arria® V GZ FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Stratix® V GX FPGA
  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The tx_cal_busy signal will not assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ, and Stratix® V GX/GT devices.

    The tx_cal_busy signal is only asserted at initial runtime calibration, or if you reset the reconfiguration controller.

    To determine whether the ATX PLL calibration process is complete you can read the ATX PLL control and status register. The busy status is bit 8 of the control and status register at address offset 7'h32.

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