Article ID: 000074766 Content Type: Troubleshooting Last Reviewed: 08/04/2023

Why does my PLL output have an incorrect phase shift in the TimeQuest timing analyzer?

Environment

  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software, the TimeQuest timing analyzer may calculate an incorrect phase shift for your PLL output clock. This problem occurs in Arria® V, Cyclone® V, and Stratix® V designs when you use derive_pll_clocks with a non-zero phase shift on the PLL reference clock. 

    Resolution

    To work around this problem, perform one of the following actions:

    • Use the phase shift setting on output clock instead of phase shifting the reference clock in your PLL.
    • Constrain the PLL outputs using the create_generated_clock constraint instead of using derive_pll_clocks.

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    Related Products

    This article applies to 15 products

    Arria® V GX FPGA
    Arria® V GT FPGA
    Cyclone® V E FPGA
    Stratix® V E FPGA
    Cyclone® V SE SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Cyclone® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Arria® V GZ FPGA
    Stratix® V GS FPGA

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