Article ID: 000084365 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Why does derive_pll_clocks fail to automatically constrain PLL output clocks?

Environment

  • Quartus® II Subscription Edition
  • PLL
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    Description Due to a problem in the Quartus® II software, the Synopsys Design Constraint (SDC) command derive_pll_clocks may not properly constrain PLL outputs. This problem occurs when your design uses PLL clock switchover in 28-nm devices, including Stratix® V, Arria® V, and Cyclone® V device. Because of this problem, the derive_pll_clocks command does not automatically create the generated clocks on PLL outputs relative to each reference clock input.