Description Due to a problem in the Quartus® II software, the Synopsys Design Constraint (SDC) command
derive_pll_clocksmay not properly constrain PLL outputs. This problem occurs when your design uses PLL clock switchover in 28-nm devices, including Stratix® V, Arria® V, and Cyclone® V device. Because of this problem, the
derive_pll_clockscommand does not automatically create the generated clocks on PLL outputs relative to each reference clock input.