Due to a problem in the Quartus® II software version 10.1 and later, the derive_pll_clocks command does not correctly constrain all clocks when using Altera_PLL with PLL clock switchover. This problem affects designs targeting Stratix® V, Arria® V or Cyclone® V devices. Instead of creating clocks associated with each input reference clock, derive_pll_clocks only creates clocks for the first reference clock.
To correctly constrain Altera_PLL outputs for each reference clock, use create_generated_clock commands as described in the document below. The document includes instructions for how to create these commands as well as example commands based on the example design below.
This problem is scheduled to be fixed in a future release of the Quartus II software.