Warning (332174): Ignored filter at <filename>.sdc: <hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0] could not be matched with a pin

You might see this warning in the Quartus® II software when compiling a design containing the the PLL Intel® FPGA IP in the Stratix® V, Arria® V, or Cyclone® V device families.
The problem occurs when you manually apply a create_generated_clock constraint for your PLL instead of using the derive_pll_clocks constraint.

The warning occurs due to PLL output counter name mismatches between the post-synthesis and post-fit netlists.

To avoid this warning, perform one of the following two actions:

• Use derive_pll_clocks to constrain your PLL.
• Use wildcards in your create_generated_clock constraint as shown below:

For an original constraint such as:

create_generated_clock -name {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|divclk} /
-source [get_pins {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco1ph[0]}]

Replace the -source reference from vco1ph[0] to vco*ph[*]:

create_generated_clock -name {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|divclk} /
-source [get_pins {<hierarchy>.gpll~PLL_OUTPUT_COUNTER|vco*ph[*]}] /

This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 13.0.