Founded in 1981, shortly after the field itself, the Very Large-Scale Integration (VLSI) Technology Symposium has always been at the helm of new developments in VLSI technology. For over 40 years, this event has provided a platform for top technologists to connect and present cutting-edge research and insights in the field. The 2022 conference runs for five days from June 13-17th. As a hybrid event this year, the symposium will offer in-person sessions in Honolulu, HI, while still providing some of the content on-demand.
Intel researchers and engineers will present 13 papers at the conference, highlighting innovations from Intel Labs, Intel Technology Development and Intel Design Engineering teams. Specifically, Intel is publishing the results of a new advanced complementary metal-oxide-semiconductor (CMOS) fin field-effect transistor (FinFET) technology, Intel 4, demonstrating more than 20% transistor performance gain at iso-power over the Intel 7 process. The Intel 4 process enables a 2x reduction in the area of the high-performance logic library, and uses extreme ultraviolet (EUV) extensively to simplify the process flow while also reducing design effort relative to Intel 7. These and the other key technology advancements presented will fuel a new generation of Intel products as Intel progresses on its roadmap set last July to introduce five process nodes in four years.
Intel is also unveiling novel methods and improvements to foundational circuits that will serve as vital components of future solutions. One such circuit innovation employs Compute Near Memory (CNM) techniques to improve the performance of an 8-core RISC-V processor and will be featured in a spotlight demo at the symposium. These and future innovations developed at Intel will not only support Intel’s product portfolio, but they are also intended to benefit customers of Intel’s new foundry business, Intel Foundry Services (IFS).
This year, Intel’s Executive Vice President and General Manager of the Accelerated Computing Systems and Graphics Group, Raja Koduri, will join the Circuits panel session, “Building the 2030 Workforce: How to attract great students and what to teach them?.” Koduri will bring unique insights from decades of experience across the tech industry.
Symposium papers will only be available to event attendees. However, abstracts for Intel’s papers, along with their session numbers are listed below. For full access to the papers, please register for the conference on the VLSI website.
A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore’s law by offering 2X area scaling of the high-performance logic library and greater than 20% performance gain at iso-power over Intel 7.
[TFS1-3] 300 mm MOCVD 2D CMOS Materials for More (Than) Moore Scaling
We demonstrate MOCVD of 2D materials directly on a 300 mm Si platform, including p-type WSe2 for the first time, for BEOL- and FEOL-application spaces. MoS2 nFETs show variability that increases with scaled geometry. Monolayer WSe2 pMOS devices achieve record ION ~100 μA/μm. We also exhibit advancement in patterned templating.
[Short Course 1] Advanced Logic Scaling Using Monolithic 3D Integration
A double-buffered, 4kb standard-cell-based register file with measured 2.4GHz operation (0.65V,100°C) and scalable performance to 3.7GHz (0.8V) is fabricated in a leading-edge CMOS node. Double-buffering, Gray-coded addressing, super-multi-bit standard cells, and mixed-frequency clocking enable peak energy-efficiency of 5.73TOPS/W (0.5V,0°C) with 14%/11% read/write power savings and 28% area reduction over conventional.
This paper presents an SRAM-based analog-Compute-in-Memory macro in 22 nm CMOS. By introducing a C-2C capacitor ladder-based charge-domain computing scheme, the proposed CiM achieves 32.2 TOPS/W and 4.0 TOPS/mm2 peak efficiency with 8-bit precision. To ensure a good multibit linearity performance, analog impairment factors were analyzed during the chip development.
[C08-1] An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS
An 8-core 64b processor extends RISC-V to perform Compute Near high-capacity last level Cache (CNC). The 1.15GHz chip expands virtual addressing, coherency, and consistency to CNC, enabling Linux-capable multi-core operation. CNC reduces energy by 52× for fully connected DNN layers. MLPerfTM Anomaly Detection latency is reduced by 4.25× to 40μs.
[C13-3] A 90.9kS/s, 0.7nJ/conversion Hybrid Temperature Sensor in 4nm-class CMOS
A PNP BJT-based temperature sensor is proposed and implemented in 4nm-class FinFET CMOS process. The design delivers fast update rates (11us) at lower power (64uW), which reach the lowest energy per conversion (0.7 nJ). It has a linear transfer function and achieves a competitive Resistive-FOM in a very small area.
[C14-3] 5G mmWave Power Amplifier and Low-Noise Amplifier in 300mm GaN‑on-Si Technology
This paper presents fully integrated power amplifier (PA) and low-noise amplifier (LNA) targeting 5G mmWave band n260 (37GHz-40GHz) in 300mm GaN‑on‑Si technology. Both circuits are compact and viable candidates for phased arrays in mobile devices. This is industry’s first demonstration of mmWave circuits in 300mm GaN‑on‑Si technology.
[C15-4] 1V CP and PGPS for IFP eFuse on Logic Technology
Intel Corporation and The University of Texas at Austin
A flexible, low-cost design solution for In-Field-Programmable (IFP) metal eFuse is presented. The design maximizes fuse yield through a tunable program voltage provided by a two-stage charge pump (CP), placed in closed-loop (CL) with low dropout regulator (LDO). This design is characterized on Intel 4 technology, with >99.9% bit success.
[C16-1] A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS
A side-channel-attack (SCA) resistant AES engine with multiplicative-masked Sboxes is fabricated in Intel 4 CMOS, achieving 1.8× lower area overhead compared to conventional additive-masked implementations. Balanced dual-rail detector circuits pre-empt zero-value attacks while providing a 34,000× increase in side-channel-attack resistance, with a measured minimum-traces-to-disclose (MTD) of 850M encryption traces.
[C19-2] A 6.0mW 3.8GS/s 7b VTC/TDC-Assisted Interleaved SAR ADC with 13GHz ERBW
Intel Labs and Nebula Microsystems
We present a hybrid ADC using one high-speed voltage-to-time converter as an interleaved SAR buffer to enhance bandwidth and remove timing skew. Time-domain encoding allows an assist TDC to enhance SAR speed. At 3.8GS/s, the 6.0mW 0.0045mm2 22nm FinFET prototype achieves 13GHz ERBW and 38dB Nyquist SNDR for 24.4fJ/step FoM.
[JFS3-4] 5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O
Intel and Ayar Labs
A first-ever realized and validated 5.12 Tbps co-packaged FPGA with optical I/O is presented. The Multi-Chip Package integrates a 14nm FPGA die with five Ayar Labs TeraPHYTM optical I/O chiplets.
[C22-1] Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSVStacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed,
Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation
A 10-tile buck IVR using 0.9nH-1.4nH 3D-TSV-based package-embedded inductors demonstrates up to 37.6% higher efficiency than LDO. Communication-free inter-tile ganging is achieved with flat efficiency over a 10mA-1A load range. Stability-aware interleaving of IVR tiles in DCM shows up to 34% reduction in output ripple compared to zero interleaving.
[C24-1] Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology
An energy-efficient high bandwidth array design using 0.0300-μm2 high performance SRAM bitcell on Intel-4 CMOS technology is presented. By employing a unique combination of design techniques, the presented 6T-SRAM array design demonstrates >80% access energy improvement over a conventional 6T-SRAM design and 30% density improvement compared to a 8T-SRAM design.
[Short Course 3-5] Auto Infotainment Evolution and Experience – A Leap Forward in IVI Experience over Time