Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Intel® FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development.The IP Core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel Quartus® Prime II design software. The package includes ModelSim precompiled library for IP Core simulation and verification.
Supports CONTROL, BULK transfer without stream support, USB2.0 backward compatible
Implementation of Link Layer & Protocol Layer, Support 16-bit and 32-bit Phy layer data interface
Implements CRC calculation and generation in hardware
All Link layer power state handling, Configurable endpoint selection
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/127.htmlFor any question or support, contact at email@example.com.
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name http://www.slscorp.com/products/development-boards/usb-3-0-development-board.html
Industry standard compliance testing performed
If No, is it planned?
IP has undergone interoperability testing
Interoperability reports available
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