USB 3.0/3.1 Gen 1 Device, Software based enumeration FIFO Interface (USB30SF)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

Stratix Series: Stratix® IV, Stratix® V


The SLS USB 3.0/3.1 Gen 1 IP Core is the SuperSpeed core that supports connectivity between TI USB 3.0/3.1 Gen 1 PHY (TUSB1310 ) and Intel® FPGA. The IP Core is wrapped around with software drivers and examples for its ease of use and quick integration. The ready to use USB 3.0 development board availability makes the integration faster. The IP Core package also contains the reference design that can be used directly for starting a custom application development.The IP Core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel Quartus® Prime II design software. The package includes ModelSim precompiled library for IP Core simulation and verification.


  • Supports CONTROL, BULK transfer without stream support, USB2.0 backward compatible
  • Implementation of Link Layer & Protocol Layer, Support 16-bit and 32-bit Phy layer data interface
  • Implements CRC calculation and generation in hardware
  • All Link layer power state handling, Configurable endpoint selection

Device Utilization and Performance


Getting Started

1. Request an Evaluation version with License from An email send to download the IP Core and the license file to compile the Intel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at any question or support, contact at

IP Quality Metrics

Year IP was first released2011
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II HAL Object Library & Application example, Windows Driver and Application example
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportWindows, Linux
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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