USB 2.0 Device with FIFO Interface (USB20HF)
Block Diagram
Overview
The USB20HF Device IP Core is USB 2.0 device core with FIFO interface for Bulk IN and Bulk OUT endpoints with ULPI interface support. The core supports three pre-configured endpoints Control, Bulk IN, and Bulk OUT. It is Configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers. Device controller communicates with the host through FIFO interface of the core. The core supports both HighSpeed (480Mbps) & FullSpeed (12Mbps) functionality.The core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel Quartus® Prime II Design Software. The package includes ModelSim pre-compiled library for core simulation and verification.
Getting Started
1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile theIntel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/114-usb20hf.htmlFor any question or support, contact at support@slscorp.com.
IP Quality Metrics
| Basic | |
|---|---|
| Year IP was first released | 2006 |
| Latest version of Quartus supported | 17.0 |
| Altera Customer Use | |
| IP has been successfully implemented in production with at least one customer | Y |
| Deliverables | |
Customer deliverables include the following:
|
Y |
| Any additional customer deliverables provided with IP | Windows Driver and Application Example |
| Parameterization GUI allowing end user to configure IP | N |
| IP core is enabled for OpenCore Plus Support | Y |
| Source language | Verilog |
| Testbench language | Verilog |
| Software drivers provided | N |
| Driver OS support | Windows, Linux |
| Implementation | |
| User Interface | Other: FIFO |
| IP-XACT Metadata included | N |
| Verification | |
| Simulators supported | Altera ModelSim |
| Hardware validated | Y. Altera Board Name http://www.slscorp.com/products/development-boards/corecommander.html |
| Industry standard compliance testing performed | N |
| If No, is it planned? | Y |
| Interoperability | |
| IP has undergone interoperability testing | N |
| Interoperability reports available | N |
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