USB 2.0 Device with FIFO Interface (USB20HF)

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Communications

Arria Series: Intel® Arria® 10, Arria® V, Intel® Arria® 10 SoC, Arria® V SoC

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


The USB20HF Device IP Core is USB 2.0 device core with FIFO interface for Bulk IN and Bulk OUT endpoints with ULPI interface support. The core supports three pre-configured endpoints Control, Bulk IN, and Bulk OUT. It is Configurable for up to 15 IN/OUT endpoints on customer request on chargeable basis. Each configurable endpoint has an endpoint controller that supports interrupt, bulk, and isochronous transfers. Device controller communicates with the host through FIFO interface of the core. The core supports both HighSpeed (480Mbps) & FullSpeed (12Mbps) functionality.The core has been optimized for Intel® FPGAs and its functionality has been verified on the hardware with Intel Quartus® Prime II Design Software. The package includes ModelSim pre-compiled library for core simulation and verification.


  • USB2.0 USBIF HighSpeed certified (TID# 70710071)
  • Supports both HighSpeed (480Mbps) FullSpeed (12Mbps) USB operation
  • FIFO Based USB 2.0 Device IP Core
  • Preconfigured for 3 endpoints - Control, Bulk In and Bulk Out
  • Configurable for up to 15 endpoints including Isochronous and Interrupt

Device Utilization and Performance


Getting Started

1. Request an Evaluation version with License from An email send to download the IP Core and the license file to compile theIntel Quartus Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at any question or support, contact at

IP Quality Metrics

Year IP was first released2006
Latest version of Quartus supported17.0
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Windows Driver and Application Example
Parameterization GUI allowing end user to configure IPN
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedN
Driver OS supportWindows, Linux
User InterfaceOther: FIFO
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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