I2C Master

Block Diagram

Solution Type: IP Core

End Market: Computer & Storage, Consumer, Industrial, Medical, Military, Test & Measurement, Wireless, Wireline

Evaluation Method: OpenCore Plus

Technology: Interface Protocols: Serial

Arria Series: Intel® Arria® 10, Arria® V

Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC

MAX Series: Intel® MAX® 10, MAX® V

Stratix Series: Stratix® IV, Stratix® V


Avalon compliant I2C Master IP core provides an interface between Nios® II processor and an I2C Slave device. It can work as a master transmitter or master receiver depending on working mode determined by Nios II processor. The I2C Master IP core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and fast-speed transmission mode.The I2C Master IP core is provided as Intel® Platform Designer (formerly Qsys) ready component and integrates easily into any Platform Designer generated system.


  • Clock stretching and wait state generation, Software programmable acknowledge bit
  • Interrupt or bit-polling driven byte-by-byte data-transfers, Arbitration lost interrupt, with automatic transfer cancellation
  • Start/Stop/Repeated Start/Acknowledge generation and detection, Bus busy detection, Supports 7 and 10bit addressing mode
  • Two transmission speeds are supported; Normal: 100Kbps Fast: 400Kbps
  • Compatible with Philips I2C standard, Multi Master Operation, Software programmable clock frequency

Device Utilization and Performance

Refer http://www.slscorp.com/ip-cores/interface/i2c-master.html

Getting Started

1. Request an Evaluation version with License from http://www.slscorp.com/licensing/ip-licensing.html.2. An email send to download the IP Core and the license file to compile the Intel Quartus® Prime II design.3. The IP Core installs documents including tutorial, software guide, reference design, Nios® II driver and examples, Windows driver and examples and testing applications.4. Integrate and test in your design.5. Reference documents are also available at http://www.slscorp.com/downloads/category/119.htmlFor any question or support, contact at support@slscorp.com.

IP Quality Metrics

Year IP was first released2007
Latest version of Quartus supported15.1
Altera Customer Use
IP has been successfully implemented in production with at least one customerY

Customer deliverables include the following:

  • Design file (encrypted source code or post-synthesis netlist)
  • Simulation model for ModelSim Altera edition
  • Timing and/or layout constraints
  • Testbench or design example
  • Documentation with revision control
  • Readme file
Any additional customer deliverables provided with IP
Nios II Example Files
Parameterization GUI allowing end user to configure IPY
IP core is enabled for OpenCore Plus SupportY
Source language
Testbench languageVerilog
Software drivers providedY
Driver OS supportNone
User InterfaceAvalon-MM
IP-XACT Metadata includedN
Simulators supportedAltera ModelSim
Hardware validated Y. Altera Board Name http://www.slscorp.com/products/development-boards/esdk.html
Industry standard compliance testing performed
If No, is it planned?Y
IP has undergone interoperability testing
Interoperability reports available  N

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