Cyclone Series: Cyclone® IV, Cyclone® V, Cyclone® V SoC
Stratix Series: Stratix® IV, Stratix® V
Supported Device Family:
SOC provides a high-performance H.264/AVC decoder IP core that supports all Intel FPGA families that have sufficient logic resources. Video transmission (UDP/IP + Ethernet) cores are available. SOC also supplies all-in-one H.264 decoder modules, which are System-on-Module (SoM) cards based on the SOC codec IP cores and Intel FPGAs.
SOC supplies plug-and-play evaluation kits for the H.264 decoder IP core.
SOC web page: http://www.soctechnologies.com/eval-kits/h264_hd_decoder_kit
IP Quality Metrics
Year IP was first released
Latest version of Quartus supported
Altera Customer Use
IP has been successfully implemented in production with at least one customer
Customer deliverables include the following:
Design file (encrypted source code or post-synthesis netlist)
Simulation model for ModelSim Altera edition
Timing and/or layout constraints
Testbench or design example
Documentation with revision control
Any additional customer deliverables provided with IP
PCB reference Designs
Parameterization GUI allowing end user to configure IP
IP core is enabled for OpenCore Plus Support
Software drivers provided
Driver OS support
IP-XACT Metadata included
Y. Altera Board Name Cyclone V, Cyclone 10, Arria V, Arria 10, Stratix IV, Stratix V
Industry standard compliance testing performed
If yes, which test(s)?
If yes, on which Altera device(s)?
If Yes, date performed
IP has undergone interoperability testing
Interoperability reports available
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